Efficient FPGAs using nanoelectromechanical relays

Chen Chen, H.-S. Philip Wong, Subhasish Mitra, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J Provine, David Lewis, Jeff Watt, Roger T. Howe
<span title="">2010</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/onq43wd7gna3zbic6lchssp6ke" style="color: black;">Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA &#39;10</a> </i> &nbsp;
Nanoelectromechanical (NEM) relays are promising candidates for programmable routing in Field-Programmable-Gate Arrays (FPGAs). This is due to their zero leakage and potentially low on-resistance. Moreover, NEM relays can be fabricated using a low-temperature process and, hence, may be monolithically integrated on top of CMOS circuits. Hysteresis characteristics of NEM relays can be utilized for designing programmable routing switches in FPGAs without requiring corresponding routing SRAM cells.
more &raquo; ... Our simulation results demonstrate that the use of NEM relays for programmable routing in FPGAs can simultaneously provide 43.6% footprint area reduction, 37% leakage power reduction, and up to 28% critical path delay reduction compared to traditional SRAM-based CMOS FPGAs at the 22nm technology node.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1723112.1723158">doi:10.1145/1723112.1723158</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/fpga/ChenPPCAPLWHWM10.html">dblp:conf/fpga/ChenPPCAPLWHWM10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rxpszxvuwfbern6llovihe6u4u">fatcat:rxpszxvuwfbern6llovihe6u4u</a> </span>
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