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Power-safe test application using an effective gating approach considering current limits
2011
29th VLSI Test Symposium
Freezing scan cell outputs can block transitions to the combinational components thus reduce shift power. The extra logic introduces area overhead, reduces timing margin and increases power in capture mode. This paper proposes a partial gating flow that calculates instance toggling probability to identify power sensitive cells. The toggling rate reduction tendency is demonstrated to be useful in estimating how much extra logic is needed to achieve a desired shift power reduction rate for a
doi:10.1109/vts.2011.5783777
dblp:conf/vts/ZhaoTC11
fatcat:nckq2ugttnfejczkzvjxt73m6i