A scarce-state-transition Viterbi-decoder VLSI for bit error correction

T. Ishitani, K. Tansho, N. Miyahara, S. Kubota, S. Kato
1987 IEEE Journal of Solid-State Circuits  
A high-speed Viterbi decoder VLSI with coding rate R = 1/2 and constraint length K = 7 for bit error correction has been developed using 1.5-pm n-well CMOS technology. To reduce both hardware size and power dissipation, a newly developed scarce-state-transition (SST) Viterbi decoding scheme has been employed. In addition, three-layer metallization and an advanced hierarchical macroeell design method (HMC~have been adopted to improve packing density and reduce chip size. As a result, active chip
more » ... area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9.52X 10.0 mmz. The VLSI decoder has achieved a maximum data throughput rate of 23
doi:10.1109/jssc.1987.1052775 fatcat:a3dnpir4yffllddgqzck7qxlry