Parallelizing sparse Matrix Solve for SPICE circuit simulation using FPGAs

Nachiket Kapre, Andre DeHon
2009 2009 International Conference on Field-Programmable Technology  
Fine-grained dataflow processing of sparse Matrix-Solve computation (A x = b) in the SPICE circuit simulator can provide an order of magnitude performance improvement on modern FPGAs. Matrix Solve is the dominant component of the simulator especially for large circuits and is invoked repeatedly during the simulation, once for every iteration. We process sparse-matrix computation generated from the SPICEoriented KLU solver in dataflow fashion across multiple spatial floating-point operators
more » ... ed to high-bandwidth on-chip memories and interconnected by a low-latency network. Using this approach, we are able to show speedups of 1.2-64× (geometric mean of 8.8×) for a range of circuits and benchmark matrices when comparing double-precision implementations on a 250MHz Xilinx Virtex-5 FPGA (65nm) and an Intel Core i7 965 processor (45nm).
doi:10.1109/fpt.2009.5377665 fatcat:22q5j5nmajdvphn7kpeo6gtsem