Experimental demonstration of an ultra-low latency control plane for optical packet switching in data center networks

Paris Andreades, Kari Clark, Philip M. Watts, Georgios Zervas
2019 Optical Switching and Networkning Journal  
A B S T R A C T Optical interconnection networks have the potential to reduce latency and power consumption while increasing the bisection bandwidth of data center networks compared to electrical network architectures. Optical circuitswitched networking has been proposed but it is reconfigurable in milliseconds. Although switches operating on nanosecond timescales have been demonstrated, centrally scheduling such switching architectures is considered to be of high complexity, incurring
more » ... nt delay penalties on the total switching latency. In this paper we present a high-speed control plane design based on a central switch scheduler for nanosecond optical switching which significantly reduces the end-to-end latency in the network compared to using the best electronic switches. We discuss the implementation of our control plane on field-programmable gate array (FPGA) boards and quantify its delay components. We focus on the output-port allocation circuit design which limits the scheduling delay and the end-to-end latency. Using our FPGA-implemented control plane, for a 32 × 32 switch, we experimentally demonstrate rack-scale optical packet switching with a minimum end-to-end head-to-tail latency of 71.0 ns, outperforming current state-of-the-art electronic switches. The effect of asynchronous control plane operation on the switch performance is evaluated experimentally. Finally, a new parallel allocation circuit design is presented decreasing the scheduling delay by 42.7% and the minimum end-to-end latency to 54.6 ns. More importantly, it enables scaling to a switch double the size (64 × 64) with a minimum end-to-end latency less than 71.0 ns. In a developed cycle-accurate network emulator we demonstrate nanosecond switching up to 60% of port capacity and average end-to-end latency less than 10 μs at full capacity while maintaining zero packet loss across all traffic loads. (P. Andreades). now replaced by flatter full-bisection bandwidth architectures [3], such as the leaf-spine shown in Fig. 1 . This topology enables scaling to high port counts while delivering full bisection bandwidth and it features low and predictable inter-rack latency as all paths are equidistant and also the shortest in length [4, 5] . However, further bandwidth scaling is limited by the number of high-speed signal pins on electronic chips [6] . Optically switched networks exploiting wavelength-division multiplexing (WDM) enable increasing the transmission capacity by orders of magnitude effectively breaking the bisection bandwidth bottleneck. Optical circuit switching has been proposed to increase the bisection bandwidth of the data center network and reduce its cost and complexity through prototypes such as c-Through [7], Helios [8], Mordia [9] and Proteus [10]. However, because the optical switches used are micro-electro-mechanical systems (MEMS), their reconfiguration time ranges from microseconds to tens of milliseconds. Hence, they are
doi:10.1016/j.osn.2018.11.005 fatcat:mnq4sidrrjfazfa6mdyplr5pta