Partial Reconfiguration in the Field of Logic Controllers Design

Michał Doligalski, Arkadiusz Bukowiec
<span title="2013-01-01">2013</span> <i title="Walter de Gruyter GmbH"> <a target="_blank" rel="noopener" href="" style="color: black;">International Journal of Electronics and Telecommunications</a> </i> &nbsp;
The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the
more &raquo; ... mic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="">doi:10.2478/eletel-2013-0042</a> <a target="_blank" rel="external noopener" href="">fatcat:jkpml6ncujcebhmccfqjzt3rse</a> </span>
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