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A two dimensional discrete wavelet transform hardware design based on canonic signed digit (CSD) architecture is presented in this paper. We have proposed canonic signed digit (CSD) arithmetic based design for low complexity and efficient implementation of discrete wavelet packet transform. Canonic signed digit (CSD) technique has been applied to reduce the number of full adders required by 2's complement based designs architecture. This architecture is suitable for application in high speeddoi:10.5120/ijca2016911926 fatcat:7qrx4fp3c5ektefiyi6bhr7d7y