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Using internal redundant representations and limited bypass to support pipelined adders and register files
Proceedings Eighth International Symposium on High Performance Computer Architecture
This paper evaluates the use of redundant binary and pipelined 2's complement adders in out-of-order execution cores. Redundant binary adders reduce the ADD latency to less than half that of traditional 2's complement adders, allowing higher core clock frequencies and greater execution bandwidth (in instructions per second). Pipelined 2's complement adders allow a higher clock frequency, but do not reduce the ADD latency. Machines with redundant binary adders are compared to machines with 2's
doi:10.1109/hpca.2002.995718
dblp:conf/hpca/BrownP02
fatcat:petjpr522jblpp2jahwyhon65e