Practical circuitry for measurement and control problems [chapter]

Jim Williams
2013 Analog Circuit Design  
The CLR1-CLK1 line monitors output voltage via the resistor string. When power is applied Q1 sets CLR2 low. This permits the LT1107 to switch, raising output voltage. When the output goes high enough Q1 sets CLR2 high and normal loop operation commences. The circuit shown is a step-up type, although any switching regulator configuration can utilize this synchronous technique. High Power 1.5V to 5V Converter Some 1.5V powered systems (survival 2-way radios, remote, transducer-fed data
more » ... systems, etc.) require much more power than stand-alone IC regulators can provide. Figure 3 's design supplies a 5V output with 200mA capacity. The circuit is essentially a flyback regulator. The LT1170 switching regulator's low saturation losses and ease of use permit high power operation and design simplicity. Unfortunately this device has a 3V minimum supply requirement. Bootstrapping its supply pin from the 5V output is possible, but requires some form of start-up Circuit operation is best understood by temporarily ignoring the flip-flop and assuming the LT1107 regulator's A OUT and FB pins are connected. When the output voltage decays the set pin drops below V REF , causing A OUT to fall. This causes the internal comparator to switch high, biasing the oscillator and output transistor into conduction. L1 receives pulsed drive, and its flyback events are deposited into the 100µF capacitor via the diode, restoring output voltage. This overdrives the set pin, causing the IC to switch off until another cycle is required. The frequency of this oscillatory cycle is load dependent and variable. If, as shown, a flip-flop is interposed in the A OUT -FB pin path, synchronization to a system clock results. When the output decays far enough (trace A, Figure 2 ) the A OUT pin (trace B) goes low. At the next clock pulse (trace C) the flip-flop Q2 output (trace D) sets low, biasing the comparator-oscillator. This turns on the power switch (V SW pin is trace E), which pulses L1. L1 responds in flyback fashion, depositing its energy into the output capacitor to maintain output voltage. This operation is similar to the previously described case, except that the sequence is forced to synchronize with the system clock by the flipflops action. Although the resulting loops oscillation frequency is variable it, and all attendant switching noise, is synchronous and coherent with the system clock. A start-up sequence is required because this circuit's clock is powered from its output. The start-up circuitry was developed by Sean Gold and Steve Pietkiewicz of LTC. The flip-flop's remaining section is connected as a buffer.
doi:10.1016/b978-0-12-397888-2.00035-3 fatcat:7jvlodovxjhztlnf4nvho5tuae