A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)

S. Eto, H. Akita, K. Isobe, K. Tsuchida, H. Toda, T. Seki
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)  
A new Delay Locked Loop (DLL) using a Digital-to-Analog Converter with the Parallel Variable Resister (PVR-DAC) has been developed. The PVR-DAC successfully manages the current controlled-delay element (CCDE) and achieves a fine time-based resolution. The DLL adopting PVR-DAC has been simulated. It realizes a time-based resolution of 18 ps, an operation frequency range of 143 MHz through 333 MHz, with the maximum power consumption of 20 mW at 1.5 V, and also achieves the small circuit area of
more » ... l circuit area of 0.5mm 2 .
doi:10.1109/apasic.2000.896980 fatcat:2glg6f3yyrbm3hpct23esznoxe