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Carbon Nanotube Based Delay Model for High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique
2014
Electrical and Electronics Engineering An International Journal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation,
doi:10.14810/elelij.2014.3404
fatcat:4xey7qf2lrccpg4aixqm52m33y