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Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based o n t r aditional fault models may not detect the actual faults in the circuit. This paper discusses the Carafe software p ackage which determines which faults are likely to occur in a circuit based o n the circuit's physical design, defect parameters, and fabrication technology.doi:10.1109/vtest.1993.313302 dblp:conf/vts/JeeF93 fatcat:cusuoaetpvaxnjaoedprl5qnji