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Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip interconnection networks that eliminates the need for buffers for routing or flow control. We describe new algorithms for routing without using buffers in router input/output ports. We analyze the advantages and disadvantages of bufferless routing and discuss how router latency can be reduced by taking advantage of thedoi:10.1145/1555754.1555781 dblp:conf/isca/MoscibrodaM09 fatcat:jndwxvbep5apnmfu374tcexzda