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Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
2007
2007 IEEE 13th International Symposium on High Performance Computer Architecture
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an alternate architecture, the Fully-Buffered DIMM. This new standard replaces the conventional memory bus with a narrow, high-speed interface between the memory controller and the DIMMs. This paper examines how traditional DDRx based memory controller policies for scheduling and row buffer management perform on a
doi:10.1109/hpca.2007.346190
dblp:conf/hpca/GaneshJWJ07
fatcat:ibrfqbstbzbgfprmhze72kfuhu