Proceedings of the 8th ACM International Systems and Storage Conference on - SYSTOR '15
Caches are integral parts in modern computers; they leverage the memory access patterns of a program to mitigate the gap between the fast processors and slow memory components. Unfortunately, the behavior of caches can be exploited by attackers to infer the program's memory access patterns, by carrying out cache-based side-channel attacks, which can leak critical information. Secure caches that were proposed employ cache partitioning or randomized memory-to-cache mapping techniques to prevent
... niques to prevent these attacks. Such techniques may add to the complexity of cache designs. In this work, we suggest the use of specialized prefetching algorithms for the purpose of protecting from cachebased side-channel attacks. Our prefetchers can be combined with conventional set associative cache designs, are simple to employ, and require low incremental hardware overhead costs, if the base prefetching scheme is already employed. We integrated our prefetching policies with commonly used GHB and stride prefetching schemes, and compared their performance with the standard implementations of those schemes, on both conventional and secure cache designs. More specifically, our results show that the use of our secure prefetching policy delivers original prefetching performance when integrated with a stride prefetcher. Finally, we demonstrate how a disruptive prefetching scheme can protect the cache from an access based side-channel attack.