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Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation
2015
2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
Specialization and accelerators are being proposed as an effective way to address the slowdown of Dennard scaling. DySER is one such accelerator, which dynamically synthesizes large compound functional units to match program regions, using a co-designed compiler and microarchitecture. We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARC-DySER), a co-designed compiler in LLVM, and a detailed performance evaluation on an FPGA system,
doi:10.1109/ispass.2015.7095806
dblp:conf/ispass/HoGNNMAFCS15
fatcat:k7lf47oavveqfiytf4qnk75j2e