Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation

Chen-Han Hoy, Venkatraman Govindarajuz, Tony Nowatzki, Ranjini Nagaraju, Zachary Marzec, Preeti Agarwal, Chris Frericks, Ryan Cofell, Karthikeyan Sankaralingam
2015 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
Specialization and accelerators are being proposed as an effective way to address the slowdown of Dennard scaling. DySER is one such accelerator, which dynamically synthesizes large compound functional units to match program regions, using a co-designed compiler and microarchitecture. We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARC-DySER), a co-designed compiler in LLVM, and a detailed performance evaluation on an FPGA system,
more » ... h runs an Ubuntu Linux distribution and full applications. Through the prototype, this paper evaluates the fundamental principles of DySER acceleration. Our two key findings are: i) the DySER execution model and microarchitecture provides energy efficient speedups and the integration of DySER does not introduce overheads -overall, DySER's performance improvement to OpenSPARC is 6×, consuming only 200mW ; ii) on the compiler side, the DySER compiler is effective at extracting computationally intensive regular and irregular code.
doi:10.1109/ispass.2015.7095806 dblp:conf/ispass/HoGNNMAFCS15 fatcat:k7lf47oavveqfiytf4qnk75j2e