Model Checking Software Architecture Design

Jiexin Zhang, Yang Liu, Jing Sun, Jin Song Dong, Jun Sun
<span title="">2012</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/tkpuwbdq2jbvrc3gixguxikkci" style="color: black;">2012 IEEE 14th International Symposium on High-Assurance Systems Engineering</a> </i> &nbsp;
Software Architecture plays an essential role in the high level description of a system design. Despite its importance in the software engineering practice, the lack of formal description and verification support hinders the development of quality architectural models. In this paper, we present an automated approach to the modeling and verification of software architecture designs using the Process Analysis Toolkit (PAT). We present the formal syntax of the Wright# architecture description
more &raquo; ... age together with its operational semantics in Labeled Transition System (LTS). A dedicated model checking module for Wright# is implemented in the PAT verification framework based on the proposed formalism. The module -ADL supports verification and simulation of software architecture models in PAT. We advance our work via defining an architecture style library that embodies commonly used architecture patterns to facilitate the modeling process. Finally, a case study of the Teleservices and Remote Medical Care System (TRMCS) modeling and verification is presented to evaluate the effectiveness and scalability of our approach.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/hase.2012.12">doi:10.1109/hase.2012.12</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/hase/Zhang00D012.html">dblp:conf/hase/Zhang00D012</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ssgbxr34ubbhbhhxe4n2fp4whi">fatcat:ssgbxr34ubbhbhhxe4n2fp4whi</a> </span>
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