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IFIP Advances in Information and Communication Technology
During a typical development process of an embedded application specific processor (ASIP), the architecture is implemented multiple times on different levels of abstractions. As a result of this redundant specification, certain inconsistencies may show up. For example, the implementation of an instruction in the simulator may differ from the HDL implementation. To detect such inconsistencies, we use register trace comparison. Our key contribution is a generic method for systematic tracedoi:10.1007/978-3-642-04284-3_19 fatcat:kurzupcbenb3zh5iz5vvuap4ly