This paper proposes a low-power and area-efficient shift register using digital pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and

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... ing additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18μm CMOS process with VDD = 1.8V. The core area is 6600μm2. The power consumption is 1.2mW at a 100 MHz clock frequency.