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Validation of an architectural level power analysis technique
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)
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This paper presents a technique used to d o p o w er analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP a n d a 3 2 -bit RISC on a single chip. Our power estimator provides power consumption data of the architecture based on the instruction data ow stream. We demonstrate the accuracy of the estimator by c o m p aring the p o w er values it produces against measurements made by a gate level power simulator for the same benchmark set. Our
doi:10.1109/dac.1998.724474
fatcat:7tn6ny4ddrggzazjs5wrz67lqu