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Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most Network Processors employ hardware accelerators for implementing key tasks. New applications require new tasks, such as pattern matching, to be performed on the packets in real-time. Using our proposed accelerator, we have implemented several such tasks and measured their performance. Specifically, the acceleratordoi:10.1109/dac.2002.1012704 fatcat:ypeyc7bi4rg4jmcovt74bidbfy