Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si

Olli-Pekka Kilpi, Johannes Svensson, Lars-Erik Wernersson
2017 2017 IEEE International Electron Devices Meeting (IEDM)  
We demonstrate a process to vary the gate-length of vertical MOSFETs on the same sample with high accuracy and high performance. Fabricated vertical InAs/InGaAs MOSFETs on Si have gate length ranging from 25 nm to 140 nm. The results shown are from single nanowire transistors as well as arrays with nanowires ranging from 80 to 500 nanowires. The devices show good yield and clear scaling trends. We demonstrate a device with gm = 2.4 mS/µm and a device with Ion = 407 µA/µm at Ioff = 100 nA/µm and
more » ... off = 100 nA/µm and VDD = 0.5 V, which both are record values for vertical MOSFETs. This is the first demonstration of vertical MOSFETs having gatelengths comparable to the state-of-the-art lateral III-V MOSFETs.
doi:10.1109/iedm.2017.8268408 fatcat:c6n6peiy7zdv5cwqobzpwteyii