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In this paper, we investigate a test strategy for characterization of clock error statistics between two clock domains in high-speed clocking systems (gigahertz and more). The method allows an indirect measurement (not based on time interval measurement) of clock error distribution by observing the integrity of a periodic sequence transmitted between two clocking domains. The method is compatible with fully on-chip implementation, and the readout of result to off-chip signals is cadenced at lowdoi:10.1109/isvlsi.2013.6654630 dblp:conf/isvlsi/ShanGA13 fatcat:qr322xpc3rhmvpsuyld2lg36au