A research into phase synchronization algorithm
Proceedings of the 2016 International Conference on Economics, Social Science, Arts, Education and Management Engineering
The research studies the carrier and timing synchronization algorithms in all-digital communication receivers. According to the optimal estimation theory of carrier phase and symbol timing synchronization technology, the estimation algorithm of the maximum likelihood carrier phases is proposed and used in computer simulations. The simulation results reveal that when the signal-noise ratio (SNR) and the observation length L meet certain requirements, the curve is highly smooth and symmetric. The
... and symmetric. The allowable minimum observation length is the capture length under this condition. If the SNR is larger than 10 dB, as for 16QAM signals, the synchronized algorithm for maximum likelihood carrier phase can track phases within 16 symbols. Introduction Traditional communication receivers use coherent demodulation to receive signals. The circuits for carrier recovery utilize Costas loop or its modified forms. While the nonlinear clock extraction method is employed in timing circuits to extract the synchronized information from the demodulated baseband signals so as to perform symbol timing and control sample collectors. The partial signals in each symbol period are sent to the balancer composed of tapped delay lines to be balanced and put into the decision device afterwards. After decision decoding, transmitting code sequences are recovered  . The typical characteristics of this communication receiver lie in that it realizes demodulation by using simulators and generates coherent clocks and carriers by controlling the voltage controlled oscillator (VCO) after feeding back the error signals of timing and carrier phases. In general, the communication receiving system which is composed of analogue devices shows many problems, such as large volume, high power consumption and cost, inconvenient debugging, easy to break down and hard to process intelligent signals. To solve these problems, the all-digital intelligent communication receivers come into being by integrating micro-electronic technology, digital signal processing technology, computer technology and communication technology. The structure of all-digital communication receivers is different from that of traditional receivers. The key difference is that the former neither uses the phase-locked loop circuit nor feeds back the signals to the simulation parts for feedback control. The work processes of full digital communication receivers are displayed as follows: Clock signals with high stability are generated by an oscillator to control the direct sampling of analog-to-digital converter (ADC) for received signals. Afterwards, the sampled and quantified digital signals are sent to the digital signal processor (DSP) system to carry out digital conversion, phase matching filter, and orthogonal matching filter, successively. In this way, the symbol timing synchronization, the recovery of carrier phases and symbol decision and decoding are implemented. Therefore, carrier and timing synchronization is the key to study all-digital communication receivers. The carrier phases and symbol timing of the all-digital communication receivers are estimated separately and jointly, which is similar to the synchronization system of analog communication receivers. This study mainly introduces the estimation algorithm of maximum likelihood carrier phases based on optimal estimation theory in separate estimation.