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With continued scaling of NAND flash memory process technology and multiple bits programmed per cell, NAND flash reliability and endurance are degrading. Understanding, characterizing, and modeling the distribution of the threshold voltages across different cells in a modern multi-level cell (MLC) flash memory can enable the design of more effective and efficient error correction mechanisms to combat this degradation. We show the first published experimental measurementbased characterization ofdoi:10.7873/date.2013.266 dblp:conf/date/CaiHMM13 fatcat:2omoug3lizfl7cijka53lwybce