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A high throughput multiplication free approximation of arithmetic coding
| Several solutions were proposed to avoid costly multiplications in approximations to arithmetic coding. These methods rely on repeated renormalizations which turn out to be the bottleneck in VLSI implementations. We propose a new renormalization scheme that achieves signi ciantly higher throughput in terms of encoded symbols per clock cycle and give some details on a VLSI implementation of this scheme.doi:10.5445/ir/156896 fatcat:vgwcahpvcnap5fmy5q3btaeeke