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Efficient ASIP design for configurable processors with fine-grained resource sharing
2008
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports
doi:10.1145/1344671.1344687
dblp:conf/fpga/DinhCW08
fatcat:baxyb7dazbf3hke3lwjbvebnj4