3D Thermal-aware floorplanner for many-core single-chip systems

David Cuesta, Jose L. Risco-Martin, Jose L. Ayala, David Atienza
2011 2011 12th Latin American Test Workshop (LATW)  
Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach; (2) an efficient Mixed Integer Linear Programming (MILP) representation of the floorplanning model; and (3) a smooth integration of the MILP model with an accurate
more » ... th an accurate thermal modelling of the architecture. The experimental work is conducted for two realistic many-core single-chip architectures: an homogeneous system resembling Intel's SCC, and an improved heterogeneous setup. The results show promising improvements of the mean, peak temperature and the thermal gradient, with a reduced overhead in the wire length of the system.
doi:10.1109/latw.2011.5985921 fatcat:hpnreptfmrdnnpx74bpx4uhrdq