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Cache Affinity Optimization Techniques for Scaling Software Transactional Memory Systems on Multi-CMP Architectures
2015
2015 14th International Symposium on Parallel and Distributed Computing
Software transactional memory (STM) enhances both ease-of-use and concurrency, and is considered one of the next-generation paradigms for parallel programming. Application programs may see hotspots where data conflicts are intensive and seriously degrade the performance. So advanced STM systems employ dynamic concurrency control techniques to curb the conflict rate through properly throttling the rate of spawning transactions. High-end computers may have two or more multicore processors so that
doi:10.1109/ispdc.2015.14
dblp:conf/ispdc/ChanLW15
fatcat:nlu7ajei7jenjmwnjhogbkpzvi