Low frequency noise in GaAs heterodimensional junction field effect transistors

N. Pala, J.-Q. Lü, M.S. Shur
2000 Electronics Letters  
An investigation is presented into the low frequency noise in GaAs heterodimensional junction field effect transistors (HD JFETs) at room and elevated temperatures. The Hooge parameter at zero gate bias was calculated to be 2 × 10 -3 for the devices. The temperature dependence of the noise was used to determine the trap level with an activation energy of 0.7eV. Recently, a new generation of semiconductor devices has emerged. These devices utilise interfaces between semiconductor regions of
more » ... tor regions of different dimensions and are called heterodimensional devices [1, 2] . One such device is the heterodimensional junction field effect transistor (HD JFET) that utilises a p + / n junction between a three dimensional p + region and two dimensional electron gas of GaAs. Studies revealed that the HD JFET has excellent characteristics at room and elevated temperatures [3, 4] . Although these features make the devices very promising for future applications at ultra-high frequencies and in low power electronics, the noise characteristics have not yet been investigated. In this Letter, we present the results of low frequency noise studies for HD JFETs. The noise measurements were performed for an HD JFET having a nominal gate length of 2 µ m and an effective gate width of 1.2 µ m. The fabrication process of the device is described in detail in [5] . The sheet density of carriers in the channel N S was 10 12 cm -2 and the extracted value of the mobility was 4000cm 2 /Vs. The extracted threshold voltage and the saturation voltage for 0.4V gate bias were -0.23 and 0.5V, respectively. The drain leakage current is of the order of 10 -9 A and the on/off drain current ratio is ~10 4 .
doi:10.1049/el:20000498 fatcat:4ogh2n5cwfcajaopybufb354um