A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2005; you can also visit the original URL.
The file type is
Address-free memory access based on program syntax correlation of loads and stores
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
An increasing cache latency in next-generation processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. One way to circumvent this cache latency problem is to predict load values at the onset of pipeline execution by exploiting either the load value locality or the address correlation of stores and loads. In this paper, we describe a new load value speculation mechanism based on the program syntax correlation of stores and loads. We establish adoi:10.1109/tvlsi.2003.812315 fatcat:6b2vs363ybdj7k5ao7cptq4sae