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VFCC: A verification framework of cache coherence using parallel simulation
2013
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
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A cache coherence protocol is a vital component of a multiprocessor to maintain the data consistency. In this paper, we proposed VFCC, which is a simulation framework to validate a cache-coherence protocol implementation of a commercial 64-bit superscalar multiprocessor. It exploits multiple-level parallelism to accelerate validation without overheads among threads. Our experimental results demonstrate VFCC has a 5.0x speedup than a traditional simulator on a conventional 16-core host machine.
doi:10.1109/aspdac.2013.6509683
dblp:conf/aspdac/XiongYSXT13
fatcat:xmhppidqgrbgrdrqvlhz27vm5m