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Basically, the denser integration capabilities will enable silicon technology scaling continuously. But in silicon technology higher variability and susceptibility will obtain. In this paper an effective network interfaces architecture if introduced for fault tolerant mechanism network on chip. A chip multi processor is introduced on chip components but this processor will not give effective output. Hence, the introduced system gives high throughput in modern network on chips. This system willdoi:10.35940/ijitee.l3949.1081219 fatcat:4iiwx365yzhbhfpujb5owdtkbm