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In this paper we explore the process of extracting potential bridging fault sites from the physical design database for VLSI devices by using standard extraction tools for fringe and overlap capacitance. We then use the extracted capacitance to create a list of potential bridging fault sites ordered to reflect the relative probability of a bridging fault occurring at each site. As a result, potential bridging fault sites can be rank-ordered for manufacturing test development such that the mostdoi:10.1109/test.2000.894272 dblp:conf/itc/StroudEBCN00 fatcat:xbqs3wujzjeutohomchzvynala