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Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
2009
Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for significant reduction in energy consumption. Our technique transforms loops containing nested conditional blocks. Specifically, the transformation takes advantage of the fact that the Boolean value of a conditional expression, determining the true/false paths, can be statically analyzed and this information, combined
doi:10.1145/1629435.1629464
dblp:conf/codes/GhodratG09
fatcat:3q3jragztvc27j5jdrugjcceli