An assigned probability technique to derive realistic worst-case timing models of digital standard cells

Alessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to
more » ... it all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method. 32nd ACM/IEEE Design Automation Conference ®
doi:10.1145/217474.217614 dblp:conf/dac/FabbroFCG95 fatcat:32mqriyl5jee5jm7n4lunmkn5a