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The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order todoi:10.1145/217474.217614 dblp:conf/dac/FabbroFCG95 fatcat:32mqriyl5jee5jm7n4lunmkn5a