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Validation and Verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to the simulation of the actual binary code using an accurate model of the processor. However, for real-time applications, the simulated execution time must be as close as possible to the execution time on the actual platform and in this case the latter gives the closest results. The main drawback of the simulation of application's softwaredoi:10.1016/j.sysarc.2012.05.001 fatcat:oyo7na2ckzbs5oi4vnor3ua4p4