Considering testability during high-level design

S. Dey, A. Raghunathan, R.K. Roy
Proceedings of 1998 Asia and South Pacific Design Automation Conference  
Considering testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate
more » ... ly testable implementations targetting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.
doi:10.1109/aspdac.1998.669447 dblp:conf/aspdac/DeyRR98 fatcat:xdnbnccq75gedi7jx53rx4cuq4