This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and circuit levels. The algorithm presents a speed up of 80x when compared to HSPICE.