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Modified CMOS Multiplication Algorithm Using Optimized Array Structure
2009
Journal of Computers
In this paper, a new, high-speed multiplication algorithm using tree circuit and a novel inner product generator has been presented. In inner product generation step, a new Smith algorithm has been modified. In inner product reduction step, a new array structure has been proposed. In final addition step, a new algorithm has been used. In this work, improvements in multiplication algorithm by using a faster counter along the tree are presented. In this paper, the novel presented multiplication
doi:10.4304/jcp.4.9.891-895
fatcat:tvw5ux2jynb6vma6vqguwsmpsq