Fault Secure Datapath Synthesis Using Hybrid Time and Hardware Redundancy

K. Wu, R. Karri
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and hardware overhead by varying these
more » ... ign parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' Behavioral Compiler. Index Terms-Concurrent error detection (CED), fault secure datapath, register transfer (RT) level synthesis, single event upset (SEU). Abstract-This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design. Index Terms-Asynchronous datapath, differential cascode voltage switch logic (DCVSL), dynamic circuits, self-checking (SC).
doi:10.1109/tcad.2004.835132 fatcat:bgymbnb2gfbthcrqj4kkryrbfm