Test development for second-generation ColdFire microprocessors

D. Amason, A.L. Crouch, R. Eisele, G. Giles, M. Mateja
1998 IEEE Design & Test of Computers  
MOTOROLA TARGETED its second-generation ColdFire family of microprocessors specifically for advanced consumer electronics applications. ColdFire products are created with a synthesis-driven, process-technology-independent, tools-based design methodology. By closely adhering to these guidelines, design teams produced four microprocessors of varying complexities: the MCF5202, MCF5203, MCF5204, and MCF-5206. J. Circello has described the ColdFire architecture. 1 This case study explains how we
more » ... loped the test methodology for ColdFire microprocessors, a methodology that evolved from test methods used for the VLSI CISC 68000 family of microprocessors. 2-5 Goals The fundamental test goals of the ColdFire processor program were low cost, a consistent methodology, automation, and accountability. Low cost. The targeted market for ColdFire products requires a low-cost test strategy that can be reduced to three major tenants. First, dedicated test circuitry must have minimal silicon area impact on the design; it was therefore allotted 5% of total area. Second, test-socket time must not exceed 5 seconds per part. Third, test program size and complexity must allow enough flexibility to operate the program on a lower cost tester. Test economics impacted every aspect of the approach. Consistent methodology. The second tenant required accurate and rapid test program generation in a regular, repeatable fashion. The objective was to implement a basic methodology to guide added complexity as it evolved. We standardized components of the methodology as much as possible to enable reuse. Automation. The key to rapid test program generation is automation. The best solution for managing a moving target must include automatic generation of test patterns. As a result, we severely limited the use of functional patterns. Accountability. Rapid test pattern generation is meaningless without a mechanism for measuring the effectiveness of the resultant patterns. Test quality is typically measured by high fault coverage levels. Beyond this statistic, however, is a fundamental responsibility to the customer to ensure that a given device meets the functional, frequency, and I/O timing specifications. Strategy By adopting carefully selected test features, test designers achieved a low-cost, repeatable, automatable, and flexible methodology resulting in high-quality measurement. This case study shows how test designers met fundamental microprocessor testing goals while adapting existing methodologies to a new architecture. DALE AMASON ALFRED L. CROUCH RENNY EISELE GRADY GILES MICHAEL MATEJA Motorola MICROPROCESSOR TESTING . JULY-SEPTEMBER 1998 71 At-speed scan. The initial scan methodology applied scan tests at the design's maximum rated frequency, a process referred to as at-speed scan. To ensure that scan vectors could be applied economically, test designers decided to use multiple parallel scan chains to minimize the number of clocks per scan test. To minimize the number of pins dedicated to test, they arranged for the scan ports of these multiple scan chains to be shared with functional pins. Designers proposed the multiplexed D flip-flop scan architecture style because it appeared to impact silicon area the least. Path delay. In the past, one of the most costly practices was the reliance on functional vectors to determine frequency and pin specifications. Using scan vectors was a more efficient way to validate frequency and pin-timing specifications and identify manufacturing defects that would limit the maximum rated frequency. The difference between these approaches was that functional vectors did not provide a timing metric, whereas scan vectors provided an implicit timing metric during automatic test-pattern generation (ATPG). The scan vectors used for AC purposes-that is, for timing specification measurements-were generated using the path delay fault model. We applied this fault model to the chip in several different ways to meet all of our timing goals. To determine the chip's operating frequency, test personnel used the path delay fault model on paths from one register (flip-flop) to another. To determine the chip's I/O specifications, they generated path delay vectors from the package primary input pins to target registers, and from target registers to package primary output pins.
doi:10.1109/54.706036 fatcat:wxlpxssoobesrdihcngbutjeje