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A case for shared instruction cache on chip multiprocessors running OLTP
2003
Proceedings of the 2003 workshop on MEmory performance DEaling with Applications , systems and architecture - MEDEA '03
Due to their large code footprint, OLTP workloads suffer from significant I-cache miss rates on contemporary microprocessors. This paper analyzes the I-stream behavior of an OLTP workload, called the Oracle Database Benchmark (ODB), on Chip-Multiprocessors (CMP). Our results show that, although, the overall code footprint of ODB is large, multiple ODB threads running concurrently on multiple processors tend to access common code segments frequently, thus exhibiting significant constructive
doi:10.1145/1152923.1024297
fatcat:5wxozscxabfrbiivwyp4a2wfgu