Motion estimation is the most computationally intensive part of video encoders, as the compression efficiency usually increases with the amount of computations. The adaptive computationally scalable motion-estimation algorithm and its hardware implementation described in this paper allow the H.264/AVC encoders to achieve efficiencies close to optimal in real-time conditions. The algorithm employs several search strategies to adapt to local motion activity, and the number of checked search

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... is set by the encoder controller for each macroblock. The algorithm can achieve results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies over time. The architecture applies a novel dataflow. First, the motion vector generation is not constrained by the calculation of residuals and corresponding costs. Second, the fractional-pel interpolation is performed prior to the integer-pel search. Third, the ME and compensation use the same resources. The architecture is verified in the real-time field-programmable gate array hardware encoder. The synthesis results and the real-time verification show that the design can support HDTV at 200 MHz for 0.13-μm TSMC technology. Index Terms-Field-programmable gate array (FPGA), H.264/AVC, motion estimation, very large-scale integration (VLSI) architecture, video coding.