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In this papel; we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive testprocedures for the faults and then show their validnesses and complexities.doi:10.1109/ats.1996.555139 dblp:conf/ats/MichinishiYOIF96 fatcat:n5t63sazfjhbjasfhu3rjdmwuy