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A structured approach to post-silicon validation and debug using symbolic quick error detection
2015
2015 IEEE International Test Conference (ITC)
During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing postsilicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. We present Symbolic Quick Error Detection (Symbolic QED), a structured approach to post-silicon validation and debug. Symbolic QED combines the following steps in a
doi:10.1109/test.2015.7342397
dblp:conf/itc/LinSBM15
fatcat:nybzktfzxrbifalzt3tfv23q44