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Timing jitter is one of the most significant phaselocked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasingdoi:10.1109/cicc.2009.5280745 dblp:conf/cicc/VamvakosSN09 fatcat:odrzxdrucbalrnyy2xsk3mkf54