Discrete-time, cyclostationary phase-locked loop model for jitter analysis

Socrates D. Vamvakos, Vladimir Stojanovic, Borivoje Nikolic
2009 2009 IEEE Custom Integrated Circuits Conference  
Timing jitter is one of the most significant phaselocked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing
more » ... jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3 rd -order PLL.
doi:10.1109/cicc.2009.5280745 dblp:conf/cicc/VamvakosSN09 fatcat:odrzxdrucbalrnyy2xsk3mkf54