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Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wiredoi:10.1145/2228360.2228391 dblp:conf/dac/ZhaoSL12 fatcat:6rxuqhebhzd7bdgewitpflg57i