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We apply algebraic tools for modelling microprocessors to the specification, implementation, and verification of an abstract pipelined case study. We employ a model of time based on counting events by means of a clock. We model systems by iterated maps that evolve over time from some initial state. We define formal correctness conditions, and introduce the one-step theorems that can reduce the complexity of formal verification. The algebraic models provide: (i) modular descriptions of pipelineddoi:10.1016/s1567-8326(03)00041-9 fatcat:fg52xyfuvngaznxligtohebar4