A three-port adiabatic register file suitable for embedded applications

Stephan Avery, Marwan Jabri
1998 Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98  
Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs, and any circuit of even moderate complexity requires some form of ram. This paper presents a register file implemented entirely with adiabatic logic, and fabricated using a 1.2 µm cmos technology. Comparison with a conventional cmos logic implementation, using both measured and simulated results, indicates significant power savings have been realised.
doi:10.1145/280756.280938 dblp:conf/islped/AveryJ98 fatcat:cv6uhe2c3fcmnork6mgf3ytoou